TECH – In a development that reads like a chapter from tomorrow’s tech manifesto, researchers at Peking University have pushed the boundaries of semiconductor science by crafting the world’s tiniest and most energy-efficient ferroelectric transistor, according to TrendForce. Their achievement — scaling the physical gate length of a ferroelectric transistor down to a mere 1 nanometer — marks a remarkable leap in memory-device engineering and could become a cornerstone for next-generation artificial intelligence hardware and ultra-efficient computing systems.
Led by Qiu Chenguang and Peng Lianmao from the School of Electronics, the research team introduced an innovative “nanogate ultra-low-power ferroelectric transistor” that operates at an astonishingly low voltage of just 0.6 volts, thanks to a novel nanogate-induced electric field concentration effect built into the device structure. At such a diminutive scale — roughly ten thousand times thinner than a human hair — the transistor’s energy consumption drops to 0.45 fJ/μm, positioning it at the frontier of low-power memory technology and heralding pathways toward sub-1 nm logic and memory integration.
Ferroelectric transistors, prized for their inherent ability to retain data without power due to reversible polarization states, have long been eyed as a leading candidate for non-volatile computing-in-memory architectures. These architectures merge storage and computational functions, offering a solution to the longstanding “memory wall” that hampers traditional systems by slowing data transfer between memory and processing units.
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Yet conventional ferroelectric designs have been hamstrung by higher operational voltages — often above 1.5 volts — which limited their compatibility with mainstream logic circuits and stalled broader adoption.
By shrinking the gate electrode to an unprecedented nanometer scale and exploiting the resulting concentrated electric fields, the Peking University team bypasses this fundamental limitation. This nanogate structure effectively lowers the energy barrier for polarization switching, enabling stable memory operation at voltages far below those once thought possible. Such ultralow-voltage operation not only enhances energy efficiency but also aligns ferroelectric memory with modern chip logic levels, making the technology far more practical for integration into future computing architectures designed for high-performance artificial intelligence workloads.
The implications ripple beyond academia: this transistor could catalyze a new generation of chips that blend memory and compute seamlessly, shrinking device footprints while cutting both energy use and latency. It may help to propel post-Moore innovations where traditional scaling slows, hinting that the next frontier in computing may not just be smaller circuits but smarter, more efficient ones.
